This article was first published in the Autumn 2014 issue of Prime
The electronic design automation (EDA) tool market has longed talked about its need to expand beyond the creation of silicon-based system-on-chips (SoCs) to provide packages that integrate the larger hardware and software system. Specifically, the major tool vendors emphasized the need to move beyond EDA-centric issues like electronic system level (ESL) design, functional verification, design-for-yield or any similar so-called crisis issues. The goal has been to move beyond chip creation to system integration to deal with both hardware and software at the chip, board and end-user product levels.
“It begins with a shift from design creation to integration in the electronic systems industry,” states the Cadence’s EDA Vision 360 report. EDA tool companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain.
Regardless of the drivers, the expansion from creation to integration tools for the larger system has not been an easy move for a variety of technical and cultural reasons. Consider but one aspect of the problem: how to provide higher-level integration when your customer uses a variety of internal and competitive tools? For example, most IDMs like Intel and Samsung, as well as fabless chip companies use a variety of EDA tools for synthesis, place and route (P&R), time and power closure, and so on. Further, many use a mix of internal tools that have been tailored to the needs of the customer.
To become a system integrator – at least from the chip design space viewpoint – tool providers will need a mechanism to gather, analyse and display useful data metrics from a variety of EDA packages. One of the few companies that come close to such an application is not an EDA company at all, but rather comes from a higher-level, product lifecycle management (PLM) provider.
Global semiconductor company Qualcomm recently shared their challenges in integrating the metrics from a mix of chip design tools. Their problem was how to put together all of the disjointed design pieces for development of its Hexagon DSP-based multithreaded CPU architecture. With a global design team (San Diego, India and Austin), the company had to communicate all of the traditional design metrics like timing and area, with secondary metrics like power and signal integrity. Adding to this technical complexity was the diversity of professionals that needed access to these metrics, from system architects, register-transfer-level (RTL) coders to logical and physical designers.
The answer was simply to use dashboards to display data and metrics in such a way as to quickly show trends and trouble spots. Good dashboards highlight the metrics data in a graphical analysis format while also providing a transition from high-level to detailed low-level views. This abstraction-level zoom-in/zoom-out capability helps designers quickly spot trouble areas and then probe down into the details.
Dashboarding is nothing new. “Qualcomm has many internal dashboards,” explained Dwight Galbi, principal manager of Qualcomm’s physical design team at a recent Dassault Systèmes’ Customer Forum. “We have dashboards that cover some of the (design metrics) … but not one that incorporated all of them.” What was needed was a dashboard to provide design metrics from a variety of EDA tools throughout the chip design process.
That’s where Dassault Systèmes’ dashboarding tool called Pinpoint came to into play. In his presentation, Galbi listed the mix of lifecycle tools (albeit from one vendor – Synopsys) used in his recent DSP project. The list included Design Compiler for synthsis; IC and Talis for P&R; and Prime Time for sign off.
“The beauty here is that these are four different tools but you can incorporate all of the reports into the same web-based server,” said Galbi. Equally important (though not mentioned by Galbi) was that the tool provides a graphical visualisation of physical design, timing paths and more, without needing to reload the entire design block. This saves both time and money since the user doesn’t need to activate a license from the EDA tool vendors. Further, using a dashboard can provide a way for geographically dispersed teams to communicate via a common view of the design. This is a key requirement for any system integration. For example, the chip’s RTL codes are often developed by teams in different geographic locations. Complicating the geographic challenges is the need to incorporate third-party IP and reused internal design blocks with the various RTL designs before the implementation process even begins. This is a problem since the physical layout and design team requires the RTL synthesised code (with all the IP), design planning and P&R data to decide if the primary chip design constraints can be met.
Getting the detailed RTL design team to work with the physical layout-design teams as soon as possible encourages communication and successful design practices. It helps mitigate the problems of siloed design activates. Also, a dashboard approach incorporates the essential data metrics from several different EDA tools into one place. This single, global view increases the likelihood of a successful SoC design as well as integrating that design – and the team – with the next level of system development.
John Blyler is an author, journalist, professor and speaker. He is also the owner/president of JB Systems. This article was taken from a Chip Design blog post
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